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 Advance Information
MC71000TB/D Rev. 2, 8/2002 MC71000 Bluetooth Baseband Controller
MC71000
Package Information Plastic Package Case 1347 (MAPBGA-100) Ordering Information
Device MC71000 Operating Temperature Range TA = - 40 to 85 C Package MAPBGA - 100
Contents
1 Applications . . . . . . . . . 2 2 Typical Bluetooth Solution Using the MC71000 2 3 Overview . . . . . . . . . . . . 3 4 Architectural Overview . . . . . . . . . . . . 4 5 Pin Assignment Listing . . . . . . . . . . . . . . 6 6 General Characteristics . . . . . . 16 7 Mechanical Specifications . . . . . . . 20 8 Functionality Overview . . . . . . . . . . . 21 9 Supported HCI Commands . . . . . . . . . 27
The MC71000 Bluetooth Baseband Controller is a part of the BluetoothTM chipset from Motorola that provides a complete, low-power Bluetooth radio system. The design is based on Motorola's third-generation Bluetooth architecture that has set the industry standard for interoperability, complete functionality, and compliance with the Bluetooth specification. The MC71000 Bluetooth Baseband Controller from Motorola implements the baseband and host controller interface (HCI) of the Bluetooth protocol. It operates with a core voltage of 1.8 V and I/Os between 1.8 V and 3.3 V. The MC71000 is the ideal solution for low-power, short-range Bluetooth applications and includes superior performance features like the dedicated Bluetooth audio processor module and on-chip memory. Debug and production test are fully supported through the joint test action group (JTAG) interface. The MC71000 provides a zero-glue logic interface for the companion MC13180 Bluetooth RF Integrated Circuit (IC), allowing the implementation of a two-chip Bluetooth Class 2 radio. The addition of the MRFIC2408 External Power Amplifier provides a Class 1 solution.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2002. All rights reserved.
Preliminary
Applications
JTAG 7
JTIC
MC71000 IPBC 32 CRM Watchdog Wakeup Clk & Reset 32 IP BUS 32 16 16 16 16 16 16 Bluetooth Link Controller Bluetooth Audio Processor UART SPI0 SPI1 TIMER GPIO SSI
VDD POR OSC 32k 2 RF 10
ARM7
MEM BID BUS 32 24 EIM 32 emCTRL ROM RAM 256K 64K
4 6 4 4 4 3
Figure 1. MC71000 Block Diagram
1 Applications
* * * * Mobile phone connectivity Personal digital assistant (PDA) connectivity Internet appliance connectivity Mobile phone headsets
2 Typical Bluetooth Solution Using the MC71000
The following figure shows a sample two-chip Bluetooth solution.
2.7 V Transceiver 1.8 V MC71000 XTAL 32 kHz XTAL 12-15 MHz
HS UART SSI SPI SPI
Baseband Controller MC71000
RF Transceiver MC13180
Figure 2. Sample Two-Chip Bluetooth Solution
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Overview
3 Overview
This section describes the overall system architecture of the MC71000 Bluetooth Baseband Controller. It highlights the main features and requirements, as well as provides an overview of the operational blocks of MC71000 Bluetooth Baseband Controller at a system level. The subsequent sections describe the detailed design requirements by major blocks and functions. The MC71000 Bluetooth Baseband Controller implements the baseband and host controller interface (HCI) of the Bluetooth protocol and is specifically designed to meet the immediate market needs for low-power Bluetooth applications. To improve the total system throughput and reduce component cost and board size, the MC71000 Bluetooth Baseband Controller integrates a Motorola-unique ARM7TDMI platform with intelligent peripheral modules focused on communications and system integration. The MC71000 Bluetooth Baseband Controller includes superior performance features for audio and power conservation, as well as debug and production test support. The MC71000 Bluetooth Baseband Controller provides a zero glue logic interface to the MC13180 Bluetooth RF Integrated CircuitC, a 2.4GHz Bluetooth radio for implementing a Bluetooth Class 2 solution. The addition of the MRFIC2408 External Power Amplifier IC provides a Class 1 solution. A power management chip, MC13181, is also available for headset and mobile phone accessory applications. The MC13181 integrates power management functions common to these applications. The architecture of the MC7100 is shown in Figure 1 on page 2.
3.1 MC71000 Bluetooth Features
* Bluetooth Specification 1.1 Compliant -- Point-to-multipoint (piconet) with 7 slaves -- All connection types -- All packet types -- All power saving modes -- Master/slave switch -- Encryption -- HCI UART transport layer * Superior Audio Performance -- Sample rate synchronization between CODEC and Bluetooth clock domains to avoid "clicking" effects -- 3 simultaneous SCO channels supported -- All Bluetooth encoding/decoding schemes supported (CVSD, A-Law, -Law) -- Very low audio delay to avoid the need for echo cancellation * Support for 8, 16, 32, and 64 kHz Sample Rate CODECs
3.2 MC71000 Hardware Features
The MC71000 is specifically designed to work with the Bluetooth protocol and supports a wide range of Bluetooth user profiles and applications. The MC71000 offers the following features: * * * * Bluetooth Link Controller Bluetooth Audio Processor ARM7 Processor Complex Peripherals
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Architectural Overview
-- High-speed UART (up to 2 Mbps) -- High-speed SSI (up to 2 Mbps) -- Dual high-speed SPI (up to 2 Mbps) * Embedded Memory -- SRAM (64K) -- ROM (256K) * * * * * External Interface Module (EIM) JTAG Test Interface Controller (JTIC) 32 kHz Oscillator (OSC32k) for Low Power Operation Operating Voltage: 1.65 V to 1.95 V Package: 100-pin MAPBGA, 7 mm x 7 mm, 0.65 mm ball pitch
4 Architectural Overview
The following sections describe the functionality and performance of the MC71000 Bluetooth Baseband Controller.
4.1 ARM7 Platform (A7P)
4.1.1 ARM7TDMI
The MC71000 Bluetooth Baseband Controller architecture is based around the 32-bit ARM7TDMI microprocessor. It is an industry-standard processor recognized for its efficient MIPS/WATT benchmark, along with excellent code efficiency when working in the 16-bit THUMB mode. The architecture is based on RISC principles and supports two instruction sets: * * The 32-bit ARM instruction set The 16-bit THUMB instruction set
4.2 Memory Sub-System
Program execution in the MC71000 Bluetooth Baseband Controller is predominantly ROM-based, with internal SRAM being used for code patching. An image can be uploaded from a host system, or a low-cost serial E2PROM (four-wire connection).
4.2.1 External Interface Module (EIM)
The external interface module (EIM) handles the interface to external devices, as well as generation of chip selects for external peripherals and memory. It contains a zero-glue interface to external memories (SRAM, E2PROM, and FLASH chips).
4.3 Peripherals Sub-System
4.3.1 Clock and Reset Module (CRM)
The clock and reset module (CRM) is dedicated to handling all clock, reset, and power management features in the MC71000 Bluetooth Baseband Controller. It assures that the different clock and reset signals are stable before they are fed to the internal logic in the MC71000 Bluetooth Baseband Controller.
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Architectural Overview
The CRM is designed to make full use of the facilities supplied by the Bluetooth standard to conserve power, while still maintaining a Bluetooth link. For this purpose, the CRM is connected to an on-chip low-power oscillator, which generates a frequency using an external low cost 32.768 kHz crystal. The CRM module also includes a watchdog to safeguard against any potential software failures.
4.3.2 Bluetooth Link Controller (BTLC)
The Bluetooth link controller module (BTLC) handles all link controller specific functions. Raw data can be read from/written to the module, and the BTLC takes care of transmission related timing, as well as data signal processing functions like encryption and cyclic redundancy check (CRC)/header error correction (HEC) generation. Embedded in the BTLC are also the dedicated Bluetooth timers, which maintain an accurate estimate of time in both the native and the remote module. A small and dedicated Bluetooth serial peripheral interface controller handles all serial communication with the MC13180 Bluetooth RF Integrated Circuit.
4.3.3 Bluetooth Audio Signal Processor (BTASP)
Special attention has been put on audio quality for the end user. For this purpose, a dedicated Bluetooth audio signal processing module (BTASP) has been designed to give users excellent and superior audio performance. With a minimum of processor intervention, this module handles all filtering, interpolation, as well as encoding/decoding (aLaw, uLaw, and CVSD).
4.3.4 High-Speed UART (up to 2 Mb/sec @ 24 MHz)
The Universal Asynchronous Receiver/Transmitter (UART) module provides one of the main interfaces to the MC71000 Bluetooth Baseband Controller. The generated baud rate is based upon a configurable divisor and input clock. It can be configured to send one or two stop bits as well as odd, even, or no parity. The UART transmit and receive buffer sizes are 32 bytes each.
4.3.5 Dual High-speed CSPI (up to 2 Mb/sec @ 24 MHz)
The MC71000 Bluetooth Baseband Controller contains two configurable serial peripheral interface (CSPI) modules, CSPI0 and CSPI1. CSPI0 can connect to a variety of SEEPROM and serial flash devices. Both CSPI modules are master/slave configurable, equipped with 16 byte data out buffers (transmit and receive FIFOs), and allow the MC71000 Bluetooth Baseband Controller to interface with external CSPI master or slave devices. Incorporating the SPIRDY and SS control signals, it enables fast data communication with a fewer number of software interrupts.
4.3.6 High-Speed SSI (up to 2 Mb/sec @ 24 MHz)
The synchronous serial interface module (SSI) is a full-duplex serial port allowing digital signal processors (DSPs) to communicate with a variety of serial devices, including industry-standard CODECs, other DSPs, microprocessors, and peripherals. The SSI is typically used to transfer samples in a periodic manner and consists of a variety of registers that handle port, status, control, transmit and receive, serial clock generation, and frame synchronization.
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Pin Assignment Listing
4.3.7 Timer (TMR)
The dual timer module (TMR) is a general purpose module, used for timing control and application-specific tasks. The TMR can also be configured to perform pulse width modulation (PWM) or put into a quadrature-count mode if needed. The TMR contains two identical 16-bit counter/timer groups, each supports counting, prescaling, comparing, loading, capturing, and holding options.
4.3.8 General Purpose (GPIO)
The MC71000 Bluetooth Baseband Controller supports a maximum of 27 GPIO lines grouped together in two ports. Port B contains 14 lines and Port C contains the other 13. These ports can be configured as GPIO pins or dedicated peripheral interface pins.
4.4 Test
4.4.1 JTAG Test Interface Controller (JTIC)
The JTIC interface offers full JTAG and boundary scan capabilities for debug and production test purposes, as well as access to the JTAG interface on the ARM.
5 Pin Assignment Listing
The following table (Table 2-1) shows the pin assignment listing for the MC71000 IC. The pins are organized into functional groups. * * * * * The Pin Name and Description columns show the actual name and a brief description of each pin. The Std Pad Drive column lists the typical (minimum) drive current required for the pin. The Power Group column lists the Supply Power Group assignment. The Reset State column lists the pin input/output direction at chip RESET. The Alternate Functions column lists each of the GPIO port alternate input and output selections available. Some selections are test- or development-mode specific.
Table 1. MC71000 Bluetooth Baseband Controller Pin Description
Pin Name Description Pin Type Reset Pull U/D EIM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line EIM - Address line O O O O O O O O O O O 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD O/L O/L O/L O/L O/L O/L O/L O/L O/L O/L O/L Std Pad Drive Power Group Reset State Alternate Functions
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Pin Assignment Listing Table 1. MC71000 Bluetooth Baseband Controller Pin Description (Continued)
Pin Name A11 D0 D1 D2 D3 D4 D5 D6 D7 CS0 CS1 OE WE Description EIM - Address line EIM - Data line EIM - Data line EIM - Data line EIM - Data line EIM - Data line EIM - Data line EIM - Data line EIM - Data line EIM - Chip Select 0 EIM - Chip Select 1 EIM - Output enable EIM - Write enable Pin Type O I/O I/O I/O I/O I/O I/O I/O I/O O O O O MISC EXTAL XTAL TRST TDI TDO TMS TCK RTCK TTS MODE0 MODE1 RESETIN CLK - 32 kHz External crystal clock input CLK - 32 kHz Crystal output JTAG - Test reset JTAG - Test data input JTAG - Test data output JTAG - Test mode select input JTAG - Test clock input JTAG - Test clock output JTAG - Test tap select Boot mode select pin 0 Boot mode select pin 1 Reset input - POR I O ST1 I Tri-O I ST1 O I I I I PU PU ST
1
Reset Pull U/D
Std Pad Drive 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA 5 mA
Power Group EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD
Reset State O/L Z/H Z/H Z/H Z/H Z/H Z/H Z/H Z/H O/H O/H O/H O/H
Alternate Functions
PU PU PU PU PU PU PU PU
-- ? PD PU ----3 mA PU PD -- -- -- -- -- -- --
MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD MISCVDD
I O I I O/L I I O I I I I
PORT A (BLUETOOTH) REFCTRL REFCLK BT1 BT2 BT3 BT4 BT5 RF Reference clock control RF Reference clock input BT - Frame synch/ CSPI_di BT - RXDATA BT - TXDATA BT - RXTXEN/ HOP_STROBE BT - SPI_CLK O I I I Tri-O O O PU 3 mA -- -- -- 3 mA 3 mA 3 mA AVDD AVDD AVDD AVDD AVDD AVDD AVDD O/L I I I Z/H O/L O/L
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Pin Assignment Listing Table 1. MC71000 Bluetooth Baseband Controller Pin Description (Continued)
Pin Name BT6 BT7 BT8 BT9 Description BT - SPI_EN BT - SPI_DO/SPI_DI BT - PWM0/TX_EN/ GPO0 BT - PWM1/PA_EN/ GPO1 Pin Type O I/O Tri-O O PORT B SSI_STCK SSI_STFS SSI_STD SSI_SRCK SSI_SRFS SSI_SRD CSPI_0_SS CSPI_0_SCK CSPI_0_MISO CSPI_0_MOSI GPIO_B10 GPIO_B11 GPIO_B12 CLK0 SSI - Serial Transmit Clock SSI - Serial Transmit Frame Sync SSI - Serial Transmit Data SSI - Serial Receive Clock SSI - Serial Receive Frame Sync SSI - Serial Receive Data CSPI #0 - Slave Select CSPI #0 - Serial Clock CSPI #0 - Master In / Slave out CSPI #0 - Master Out / Slave in General Purpose I/O General Purpose I/O General Purpose I/O Programmable Clock Output I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I/O PU PU PU PU PU PU PU PU PU PU PU PU PU PU PORT C TXD CTS_ RXD RTS_ CSPI_1_SS UART - TXD UART - CTS UART - RXD UART - RTS CSPI #1 - Slave select Tri-O Tri-O I/O I/O O PU PU PU PU PU 3 mA 3 mA 3 mA 3 mA 3 mA CVDD CVDD CVDD CVDD CVDD Z/H Z/H Z/H Z/H O/H GPIO_C0; CSPI0_REQ GPIO_C1; CSPI1_REQ GPIO_C2; TIM_0_I GPIO_C3; TIM_1_I GPIO_C4; SYSCLK 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD Z/H Z/H Z/H Z/H Z/H Z/H Z/H Z/H O/L Z/H Z/H Z/H Z/H O/L GPIO_B0; BT_TP0 GPIO_B1; BT_TP1 GPIO_B2; BT_TP2 GPIO_B3; BT_TP3 GPIO_B4; BT_TP4 GPIO_B5; BT_TP5 GPIO_B6; BT_TP6 GPIO_B7; BT_TP7 GPIO_B8; BT_TP8; GPIO_B9; BT_TP9 GPIO_B10 UART-TXD GPIO_B11 UART-RTS GPIO_B12 UART-RXD GPIO_B13 UART-CTS Reset Pull U/D Std Pad Drive 3 mA 3 mA 3 mA 3 mA Power Group AVDD AVDD AVDD AVDD Reset State O/H O/L O/L O/L Alternate Functions
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Pin Assignment Listing Table 1. MC71000 Bluetooth Baseband Controller Pin Description (Continued)
Pin Name Description Pin Type O I/O I/O I/O I/O I/O I/O I/O Reset Pull U/D PU PU PU PU PU PU PU PU Std Pad Drive 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA Power Group CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD Reset State O/H O/L Z/H O/L Z/H O/L O/L O/L Alternate Functions GPIO_C5; SH_STROBE GPIO_C6; ABORT GPIO_C7; REFCLK GPIO_C8; TIM_0_O GPIO_C9; XACK GPIO_C10; TIM_1_O GPIO_C11 GPIO_C12
CSPI_1_SCK CSPI_1_MISO CSPI_1_MOSI CLK1 GPIO_C9 OSC32K SYSCLK BTCLK
CSPI #1 - Serial clock CSPI #1 - Master In / Slave out CSPI #1 - Master Out / Slave in Programmable clock output General Purpose I/O Buffered Low Power 32 kHz Clock Buffered System Clock Buffered Bluetooth Clock
EIM POWER/GROUND GND_EIM2 GND_EIM3 GND_EIM4 GND_EIM6 GND_EIM7 PWR_EIM2 PWR_EIM3 PWR_EIM4 PWR_EIM6 PWR_EIM7 GND GND GND GND GND PWR PWR PWR PWR PWR GND GND GND GND GND PWR PWR PWR PWR PWR MISC POWER/GROUND GND_MISC PWR_MISC GND PWR GND PWR PORT A POWER/GROUND GND_PA PWR_PA GND PWR GND PWR PORT B POWER/GROUND GND_PB PWR_PB GND PWR GND PWR PORT C POWER/GROUND GND_PC PWR_PC GND PWR GND PWR CORE POWER/GROUND GND_CORE1 GND_CORE2 GND_CORE3 GND GND GND GND GND GND COREVDD COREVDD COREVDD CVDD CVDD BVDD BVDD AVDD AVDD MISCVDD MISCVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD EIMVDD
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Pin Assignment Listing Table 1. MC71000 Bluetooth Baseband Controller Pin Description (Continued)
Pin Name GND_CORE4 GND Description Pin Type GND PWR PWR PWR PWR Reset Pull U/D Std Pad Drive Power Group COREVDD COREVDD COREVDD COREVDD COREVDD Reset State Alternate Functions
PWR_CORE1 PWR PWR_CORE2 PWR PWR_CORE3 PWR PWR_CORE4 PWR 1.ST - Schmitt Trigger input
5.1 Pin Descriptions
The following table provides detailed pin descriptions for the external interface module (EIM); clock, reset, and JTAG; Bluetooth; SSI, SPI0, and UART; and UART, SPI1, and TIM including the GPIO shared package pins. In the following table, the general purpose input/output (GPIO) is designed to share package pins with other peripheral modules on the chip. If the peripheral which normally controls a given pin is not required, then the pin may be programmed to be a general purpose input/output (GPIO) or alternate function 2 with programmable pullup. The GPIO module design has two available ports (Port B and Port C). The individual control for each pin can be in normal functional mode, alternate function mode 2, or GPIO mode. The individual direction control for each pin is in GPIO mode. The individual pullup enable control for each pin is in normal function mode, alternate function mode 2, or GPIO mode. * * * Normal mode. The peripheral module controls the output enable and any output data to the pad and any input data from the pad is passed to the peripheral. Alternate function 1 mode (GPIO). The GPIO module controls the output enable to the pad and supplies any data to be output. Alternate function 2 mode. The peripheral module controls the output enable and any output data to the pad and any input data from the pad is passed to the peripheral.
Table 2. Pin Descriptions
EIM Signals Active high, bidirectional inputs/outputs. D0 is the least significant bit and D7 is the most significant. These pins provide the bidirectional data bus for external memory access. D0-D7 are held in the previous logic state when there is no external bus activity. This is done with weak "keepers" inside the I/O buffers. They are also kept in their previous state during hardware reset. Active high outputs, specifies the address for external memory accesses. ADDR0 is the least significant bit and ADDR11 is the most significant. To minimize power dissipation, ADDR0-ADDR11 do not change state when external memory is not being accessed. This output signal is active low and is asserted based on the decode of the internal address bus. This active-low output signal is asserted based on the decode of the internal address bus. This active low output signal is used to indicate that the bus access is a read and enables slave devices to drive the data bus with read data. OE is negated during hardware reset. This active low output signal is used to indicate that the bus access is a write and enables slave devices to drive the address bus with the write data.
D0-D7 (Data Bus)
A0-A11 (Address Bus)
CS1 (Chip Select 1) CS0 (Chip Select 0)
OE (Output Enable)
WE (Write Enable)
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Pin Assignment Listing Table 2. Pin Descriptions (Continued)
Clock, Reset, and JTAG Signals EXTAL CLK XTAL CLK TDI (Test Data Input) 32 kHz external crystal clock input 32 kHz Crystal output The test data input pin provides a serial input data stream to all TAP controllers. TDI is sampled on the rising edge of TCK. The test data output pin is tri-statable, providing serial output data from the Master TAP or ARM Core TAP controller. It is actively driven in the shift-IR and shift-DR controller states of the TAP controller state machine. TDO changes on the falling edge of TCK. This active low Schmitt trigger input pin provides an asynchronously reset signal to all TAP controllers to initialize the test controller. The test mode select input pin is used to sequence all TAP controllers. The TAP sequenced is determined by the tap control module and the TTS device port. TMS is sampled on the rising edge of TCK. The test clock input pin is used to synchronize the JTAG test logic. It provides the clock to synchronize the test logic and shift serial data to and from all TAP controllers. The return test clock input pin returns the synchronization test clock to ARM development tools to be entered from the serial debug input line. The test tap select input pin directly controls the multiplexing logic to select between the chip TAP and the core TAP. A logic 1 applied to the tap select input will select the chip TAP. Test/boot mode select pins. In order to support a flexible development system, the system must be capable to boot from different memories during system reset and power-up. The four different memory maps can be selected by these two pins. All the different boot modes start reading data at address 0x0000_0000, since this is where the ARM7 reset vector is located. The reset in pin is an active low Schmitt trigger input that provides reset to the internal circuitry. The RESET input will be qualified as valid if it will be asserted for at least 3 CLK cycles. Bluetooth Signals REFCTRL (Reference Control) REFCLK (Reference Clock) BT1 BT2 BT3 BT4 BT5 BT6 The reference control pin is a dedicated output from the CRM which enables/disables the reference clock. The reference clock pin is a dedicated input into the CRM from the RF interface. (12-32 MHz) Input from the RF front end. Frame sync for the MC13180 RF IC; CSPI_din for Silicon Wave RXDATA: Input from the MC13180 RF IC and Silicon Wave RF Front End TXDATA: Output to the MC13180 RF IC and Silicon Wave RF Front End Dedicated RF control output to the RF Front Ends. RXTX_EN for the MC13180 RF IC Radio or HOP_STROBE for the Silicon Wave Radio. CSPI_CLK: One of the three CSPI signals which program the MC13180 RF IC Radio or one of the four CSPI signals which program the Silicon Wave Radio. CSPI_EN: One of the three CSPI signals which program the MC13180 RF IC Radio or one of the four CSPI signals which program the Silicon Wave Radio. CSPI_DOUT/CSPI_DIN: One of the three CSPI signals which program the MC13180 RF IC Radio (CSPI_DIN or CSPI_DOUT) or one of the four CSPI signals which program the Silicon Wave Radio (CSPI_DOUT)
TDO (Test Data Output)
TRST (Test Reset)
TMS (Test Mode Select)
TCK (Test Clock) RTCK (Return Test Clock)
TTS (Test TAP select)
MODE[1:0]
RESETIN (Reset In)
BT7
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Pin Assignment Listing Table 2. Pin Descriptions (Continued)
BT8 The BT8 pin is a RF control output which can be programmed for different purposes, such as TX_EN, PWM0 (Pulse Width modulator output), or as GPO0. The BT9 pin is an RF control output which can be programmed for different purposes, such as PA_EN (power amplifier enable), PWM1 (pulse width modulator output) or as GPO1. SSI, SPI0, and UART Signals SSI_STCK/GPIO_B0/BT_TP0 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 SSI_STFS/GPIO_B1/BT_TP1 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 SSI_STD/GPIO_B2/BT_TP2 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 SSI_SRCK/GPIO_B3/BT_TP3 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 SSI_SRFS/GPIO_B4/BT_TP4 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 SSI_SRD/GPIO_B5/BT_TP5 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CSPI_0_SS/GPIO_B6/BT_TP6 SSI_SRD GPIO_B5 BT_TP5 The serial receive data signal is used to receive serial data. GPIO 5 on Port B Bluetooth test port signal SSI_SRFS GPIO_B4 BT_TP4 The serial receive frame sync signal is used by the receiver to synchronize the transfer of data. The frame sync signal can be one bit or one word in length. GPIO 4 on Port B Bluetooth test port signal SSI_SRCK GPIO_B3 BT_TP3 The serial receive clock signal is used by the receiver and is always continuous, however, it is not used in synchronous mode. GPIO 3 on Port B Bluetooth test port signal SSI_STD GPIO_B2 BT_TP2 The serial transmit data signal is used to transmit serial data. GPIO 2 on Port B Bluetooth test port signal SSI_STFS GPIO_B1 BT_TP1 The serial transmit frame sync signal is used by the transmitter to synchronize the transfer of data. The frame sync signal can be one bit or one word in length. GPIO 1 on Port B Bluetooth test port signal SSI_STCK GPIO_B0 BT_TP0 The serial transmit clock signal is used by the transmitter and can be either continuous or gated. GPIO 0 on Port B Bluetooth test port
BT9
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Pin Assignment Listing Table 2. Pin Descriptions (Continued)
Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CSPI_0_SCK/GPIO_B7/BT_TP7 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CSPI_0_MISO/GPIO_B8/BT_TP8 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CSPI_0_MOSI/GPIO_B9/BT_TP9 Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 GPIO_B10/UART_TxD Alternate Function 1 (GPIO) Alternate Function 2 GPIO_B11/UART_RTS Alternate Function 1 (GPIO) GPIO_B11 GPIO 11 on Port B UART ready to send (RTS) This input signal, when asserted, indicates that the remote device is ready to accept new data and that the MC71000 Bluetooth Baseband Controller can transmit when it has data to send. GPIO_B10 UART_TxD GPIO 10 on Port B Transmit data serial (output signal) CSPI0 GPIO_B9 BT_TP9 Master Out Slave In: In master mode, this bidirectional signal is the TXD output signal. In slave mode, MOSI is the RXD input signal. GPIO 9 on Port B Bluetooth test port signal; Bluetooth 4 MHz clock CSPI0 GPIO_B8 BT_TP8 Master In Slave Out: In master mode, this bidirectional signal is the RXD input signal. In slave mode, MISO is the TXD output signal. GPIO 8 on Port B Bluetooth test port signal CSPI0 Clock GPIO_B7 BT_TP7 This bidirectional signal is the CSPI0 clock output in master mode. In slave mode, CSPI_0_SCK is an input clock signal to the CSPI. GPIO 7 on Port B Bluetooth test port signal CSPI_0_SS GPIO_B6 BT_TP6 The CSPI0 slave select bidirectional signal is an output in master mode and an input in slave mode. GPIO 6 on Port B Bluetooth test port signal
Alternate Function 2
UART_RTS
GPIO_B12/UART_RxD Alternate Function 1 (GPIO) Alternate Function 2 CLK0/GPIO_B13/UART_CTS Output to external devices generated by the fractional clock divider in the CRM. CLK0 is a programmable clock and derivative of REFCLK. Frequencies are programmable in the range of REFCLK/127 to REFCLK. CLK0 can be used to feed an external USB, a CODEC, or whatever the applications need. The fractional divider has 16-bit resolution; writing 0x000 to the divisor disables the timer. GPIO_B12 UART_RxD GPIO 12 on Port B Receive data serial (input signal)
Normal Mode
CLK0
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Pin Assignment Listing Table 2. Pin Descriptions (Continued)
Alternate Function 1 (GPIO) GPIO_B13 GPIO 13 on Port B UART clear to send (CTS) This output signal, when asserted, indicates that the MC71000 Bluetooth Baseband Controller is ready to accept new data and the remote device can transmit when it has data to send.
Alternate Function 2
UART_CTS
UART, SPI1, and TIM Signals TXD/GPIO_C0/CSPI0_REQ Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CTS/GPIO_C1/CSPI1_REQ UART clear to send (CTS) output signal, when asserted, indicates that the MC71000 is ready to accept new data and the remote device can transmit when it has data to send. GPIO 1 on Port C External data transfer rate control for CSPI1 TXD GPIO_C0 CSPI0_REQ UART transmit data serial (output signal) GPIO 0 on Port C External data transfer rate control for CSPI0
Normal Mode
CTS
Alternate Function 1 (GPIO) Alternate Function 2 RXD/GPIO_C2/TIM_0_I Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 RTS/GPIO_C3/TIM_1_I
GPIO_C1 CSPI1_REQ
RXD GPIO_C2 TIM_0_I
UART receive data serial (input signal) GPIO 2 on Port C Input signal to timer 0
Normal Mode
RTS
UART ready to send (RTS) input signal, when asserted, indicates that the remote device is ready to accept new data and that the MC71000 can transmit when it has data to send. GPIO 3 on Port C Input signal to timer 1
Alternate Function 1 (GPIO) Alternate Function 2 CSPI_1_SS/GPIO_C4/SYSCLK Normal Mode Alternate Function 1 (GPIO)
GPIO_C3 TIM_1_I
CSPI1 GPIO_C4
Slave Select: This bidirectional signal is an output in master mode and an input in slave mode. GPIO 4 on Port C System clock used by the entire ARM7 platform and all peripherals attached to the IP and AHB bus. Some of the peripherals (for example, UART) will also use this clock signal to generate their own module clock.
Alternate Function 2
SYSCLK
CSPI_1_SCK/GPIO_C5/SH_STROBE Normal Mode Alternate Function 1 (GPIO) CSPI Clock GPIO_C5 This bidirectional signal is the CSPI clock output in master mode. In slave mode, CSPI1_SCK is an input clock signal to the CSPI. GPIO 5 on Port C
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Pin Assignment Listing Table 2. Pin Descriptions (Continued)
Alternate Function 2 CSPI_1_MISO/GPIO_C6/ABORT Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CSPI_1_MOSI/GPIO_C7/REFCLK Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 CLK1/GPIO_C8/TIM_0_O Output to external devices generated by the integer divider. CLK1 is a programmable clock and derivative of REFCLK. Frequencies are programmable in the range of REFCLK/64 to REFCLK. CLK1 can be used to feed an external USB, a CODEC, or whatever device the applications need. The integer divider should divide REFCLK with (1, 2, 4, 8, 16, 32, or 64). The value 0 disables the timer. GPIO 8 on Port C Output signal from timer 0 CSPI1 GPIO_C7 REFCLK Master Out Slave In (MOSI): In master mode, this bidirectional signal is the TXD output signal. In slave mode, MOSI is the RXD input signal. GPIO 7 on Port C RF reference clock input (12-32 MHz) CSPI1 GPIO_C6 ABORT Master In Slave Out (MISO): In master mode, this bidirectional signal is the RXD input signal. In slave mode, MISO is the TXD output signal. GPIO 6 on Port C Indicates the current memory access can not be completed. SH_STROBE Indicates data is valid on the external bus when show cycle is used.
Normal Mode
CLK1
Alternate Function 1 (GPIO) Alternate Function 2 GPIO_C9/XACK Alternate Function 1 (GPIO) Alternate Function 2 OSC32K/GPIO_C10/TIM_1_O Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 SYSCLK/GPIO_C11/A20
GPIO_C8 TIM_0_O
GPIO_C9 XACK
GPIO 9 on Port C External acknowledge signal
OSC32K GPIO TIM_1_O
Buffered output from 32 kHz on chip oscillator GPIO 10 on Port C Output signal from timer 1
Normal Mode
SYSCLK
System clock used by the processor as well as most peripherals attached to the IP and AHB bus. Some of the peripherals (for example, BTLC) will derive their internal clock based on the SYSCLK. GPIO 11 on Port C Address line signal used for debugging
Alternate Function 1 (GPIO) Alternate Function 2 BTCLK/GPIO_C12/A21
GPIO_C11 A20
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General Characteristics Table 2. Pin Descriptions (Continued)
Normal Mode Alternate Function 1 (GPIO) Alternate Function 2 BTCLK GPIO_C12 A21 The Bluetooth 4 MHz system clock, used internally in all Bluetooth-related calculations. GPIO 12 on Port C Address line signal used for debugging
5.1.1 Power and Ground
The following table shows the power and ground supplies.
Table 3. Power and Ground Supplies
Name COREVDD AVDD BVDD CVDD MISCVDD EIMVDD Description Core Supply Port A Noise Sensitive Bluetooth Supply Port B Supply Port C Supply Clock and JTAG Supply EIM Supply Value 1.8 V 1.8 V 1.8 - 3.3 V 1.8 - 3.3 V 1.8 V 2.7 V1
1.Can run at 1.8 V with degraded performance in timing and pull-ups
NOTE:
All pads are tolerant to 3.6 V. All ground supplies are tied together.
5.2 Functional Grouping of Signals Polaris
I/O Pad I/O Pad I/O Pad
1.8 V
I/O Pad I/O Pad
Port A - Bluetooth
EIM
2.7 V
Core 1.8 V
1.8 - 3.3 V
Port B - SSI, SPI0, TIM, GPIO
MISC
1.8 V 1.8 V
I/O Pad
1.8 - 3.3 V
Port C - UART, SPI1, TIM, GPIO
Core
Figure 3. Functional Grouping of Signals
6 General Characteristics
Absolute maximum ratings given in Table 4 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device.
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General Characteristics
The MC71000 DC/AC electrical specifications are preliminary and are from design simulations and analysis. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed.
WARNING:
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to the high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either or VCC or GND).
Table 4. Absolute Maximum Ratings (GND = 0 V)
Rating Core supply voltage All other input voltages Storage temperature range Symbol VDD VIN TSTG Value (GND-0.3) to 2.0 (GND - 0.3) to 3.6 -55 to 150 Unit V V C
Table 5. Recommended Operating Conditions
Characteristic Core supply voltage Ambient temperature Symbol VDD TA Min 1.65 -40 Typ 1.8 -- Max 1.95 85 Unit V C
Table 6. Package Thermal Characteristics
Thermal Resistance Junction-to-ambient (estimated)1 Junction-to-case (estimated)2 Symbol RJA RJC 181-pin PGA 105.38 28.76 100-pin MAPBGA 22 1.6 Unit C/W C/W
1.Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided Printed Circuit Board. 2.Junction-to-case thermal resistance is based on measurements using a cold plate per with the exception that the cold plate temperature is used for the case temperature.
6.1 DC Electrical Characteristics
Table 7.
Characteristics EIM supply voltage MISC supply voltage Bluetooth supply voltage (Port A)
DC Electrical Characteristics
Min -- 1.8 -- Typ 2.7 -- 1.8 Max -- 3.3 -- Unit V V V
Symbol EIMVDD MISCVDD AVDD
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General Characteristics Table 7.
Characteristics Supply voltage (level shift I/O) High-level DC input voltage EIMVDD (2.7 V) MISCVDD AVDD BVDD CVDD High-level DC output voltage (2.7 V) EIMVDD MISCVDD AVDD BVDD CVDD Low-level DC output voltage Low-level DC input voltage Current drain (run mode) @ 24 MHz, 1.8V Current drain (stop mode) @ 1.8V Input capacitance (estimated) VOL VIL IDDACTIVE IDDSLEEP CIN VOH 2.2 MISCVDD * AVDD * 0.8 BVDD * 0.8 CVDD * 0.8 0 -.3 -- -- -- -- -- -- -- -- 17 2.7 1.8 AVDD BVDD CVDD VDD * 0.2 VDD * 0.2 -- V V mA A pF V VIH 1.90 MISCVDD * AVDD * 0.8 BVDD * 0.8 CVDD * 0.8 2.7 1.8 -- -- -- 3.6 3.6 3.6 3.6 3.6 V
DC Electrical Characteristics (Continued)
Symbol BVDD CVDD Min 1.8 Typ -- Max 3.3 Unit V
-- --
25 5
-- --
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General Characteristics
VDD VSS
13 13
Power Port Ground Port
REFCTRL REFCLK BT1 - Frame Synch/SPI_di
EXTAL XTAL RESETIN Clock and Reset BT Port
BT2 - RxData BT3 - TxData BT4 - RxTxEn/Hop_strobe BT5 - CSPI_clk
CLK0 (GPIO_B13) CLK1 (GPIO_C8) OSC32K (GPIO_C10) SYSCLK (GPIO_C11) BTCLK (GPIO_C12) Programmable Clock Output or GPIO
BT6 - CSPI_en BT7 - CSPI_do/CSPI_di BT8 - PWM0/Tx_en/GPO0 BT9 - PWM1/PA_en/GPO1 SSI_STCK (GPIO_B0) SSI_STFS (GPIO_B1)
A[11:0] D[7:0]
12 8
External Address Bus External Data Bus
SSI Port or GPIO
SSI_STD (GPIO_B2) SSI_SRCK (GPIO_B3) SSI_SRFS (GPIO_B4)
CS[1:0] OE WE
2 SPI0 Port or GPIO
SSI_SRD (GPIO_B5) CSPI_0_SS (GPIO_B6) External Bus Control CSPI_0_SCK (GPIO_B7) CSPI_0_MISO (GPIO_B8) CSPI_0_MOSI (GPIO_B9)
TRST GPIO TDI TDO TMS TCK RTCK TTS MODE0 MODE1 SPI1 Port or GPIO JTAG Port
4 GPIO_B10 - GPIO_B12, GPIO C UART_TXD (GPIO_C0)
UART Port or GPIO
UART_CTS (GPIO_C1) UART_RXD (GPIO_C2) UART_RTS (GPIO_C3) CSPI_1_SS (GPIO_C4) CSPI_1_SCK (GPIO_C5) CSPI_1_MISO (GPIO_C6) CSPI_1_MOSI (GPIO_C7)
MODE Pins
Figure 4. 100 MAPBGA Standard Configuration
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Mechanical Specifications
7 Mechanical Specifications
7.1 Packaging
MAPBGA, 100-pin * * 7 mm x 7 mm x 1.35 mm 0.65 mm pitch
Table 8. MC71000 Bluetooth Baseband Controller 100 MAPBGA Ball Pad to Signal Name Net List
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4
A6 A2 CS0 WE CTS SPI1_SCK RXD RTS SSI_STCK SSI_SRCK A7 A5 A0 OE TXD SPI1_MISO PWR_PC3 SPI0_SS SSI_STD SSI_SRD A9 A8 CS1 PWR_CORE4 GPIO_C9 SPI1_MOSI GND_PC3 PWR_PB2 SSI_STFS SSI_SRFS A11 A10 A3 GND_CORE4
D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8
OSC32K SPI1_SS BTCLK GND_PB2 SPI0_SCK SPI0_MOSI PWR_EIM2 GND_EIM2 PWR_EIM7 A1 CLK1 SYSCLK GPIO_B11 SPI0_MISO CLK0 GPIO_B12 D0 PWR_CORE1 GND_CORE1 GND_EIM7 A4 MODE1 GPIO_B10 PWR_CORE3/ GND_CORE3/ RESETIN D3 D4 D2 D1 GND_PA1 GND_MISC1 TCK TTS
G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
MODE0 PWR_IO_I1_MISC D6 D7 D5 GND_CORE2 PWR_PA1 BT8 BT9 TMS TDO RTCK GND_EIM3 GND_EIM4 GND_CORE2 PWR_CORE2 BT7 REFCLK BT2 BT4 EXTAL TDI PWR_EIM3 PWR_EIM4 PWR_CORE2 REFCTRL BT6 BT5 BT1 BT3 XTAL TRST
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Functionality Overview
Figure 5. 100 MAPBGA Package Diagram 7 mm x 7 mm x 1.35 mm
8 Functionality Overview
The following section describes the link control and link manager features in detail and provides information on when those features will be supported (if not supported in this version).
8.1 Link Control Features
The following table lists, in detail, the supported link controller features of the MC71000. With only slight modification, the table has been prepared so that it closely parallels the Bluetooth SIG's PICS Proforma Annex B, Version 0.91.
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Functionality Overview Table 9. Overview of Link Controller Features
ROM V0.92 and ROM V2.01 Frequency Hopping Systems Planned Future Features Support Not Currently Planned
Feature
79-channel frequency hopping system 23-channel frequency hopping system
2
x x
Link Types
ACL link support SCO link support
x x
Piconet Capabilities
Max simultaneous ACL links3 Point-to-point connection Point-to-multipoint connections
7 x x
Scatternet Capabilities
7
Master in one piconet and slave in another Slave in more than one piconet
SCO Link Capabilities
Max simultaneous SCO links3 Multiple SCO links to same slave Multiple SCO links to different slaves Multiple SCO links from same master Multiple SCO links from different masters
1
3
x
Common Packet Types
ID packet type NULL packet type POLL packet type FHS packet type DM1 packet type
x x x x x
ACL Packet Types
DH1 packet type DM3 packet type DH3 packet type DM5 packet type DH5 packet type AUX1 packet type
x x x x x x
SCO Packet Types
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Functionality Overview Table 9. Overview of Link Controller Features (Continued)
ROM V0.92 and ROM V2.01 Planned Future Features Support Not Currently Planned
Feature
HV1 packet type HV2 packet type HV3 packet type DV packet type
x x x x
Paging Procedures
Paging, 79-channel system Page scan, 79-channel system Paging, 23-channel system2 Page scan, 23-channel system
2
x x x x
Paging Schemes
Paging scheme 0 (Mandatory) Paging scheme 1 (Optional I)
x
Page Scanning Modes
Paging mode R0 Paging mode R1 Paging mode R2
x x x
Paging Train Repetition
Npage 1 Npage 128 Npage 256
x x x
Inquiry Procedures
Inquiry, 79-channel system Inquiry scan, 79-channel system Inquiry, 23-channel system2 Inquiry scan, 23-channel system Inquiry support for all IACs Inquiry scan, max num simultaneous IACs
2
x x x x x 2 2
Other Link Controller Features
Transparent SCO data pass-through Adaptive Frequency Hopping Antenna diversity 1.ROM V2.0 is the label assigned to the production-ready, qualified iteration of ROM Version 0.92. There is no plan for a "ROM V1.0". 2.The 23-channel frequency hopping system is fully implemented in ROM Version 0.92, but as it is being discontinued by the Bluetooth SIG, extensive testing has not been performed.
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Functionality Overview
3.This value can be adjusted down to reduce the amount of RAM consumed on the MC71000.
8.2 Link Manager Features
Table 10 lists the Link Manager features of the MC71000. The table parallels the Bluetooth SIG's PICS Proforma Annex C, Version 0.91.
Table 10. Overview of Link Manager Features
ROM V0.92 and ROM V2.01 Supported Features (General Statement) Planned Future Features Support Not Currently Planned
Feature
3-slot packets 5-slot packets Encryption Slot offset Timing accuracy Role switch (master/slave) Hold mode Sniff mode Park mode Power control Channel quality driven data rate RSSI
Authentication
x x x x x x x x x x x x
Initiate authentication before connection completed Initiate authentication after connection completed Respond to authentication request
Pairing
x x x
Initiate pairing before connection completed Initiate pairing after connection completed Respond to pairing request Use fixed PIN and request responder-to-initiator switch Use variable PIN Accept initiator-to-responder switch
Link Keys
x x x x x x
Link key creation using a unit key (local device is configured with a unit key) Link key creation using a unit key (remote device is configured with a unit key) x
x
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Functionality Overview Table 10. Overview of Link Manager Features (Continued)
ROM V0.92 and ROM V2.01 Planned Future Features Support Not Currently Planned
Feature
Link key creation using a combination key Initiate change of link key Accept change of link key Change to temporary key (i.e., master link key) Make semi-permanent link key the current link key (i.e., exit master link key)
Encryption
x x x x x
Initiate encryption Accept encryption requests Point-to-point encryption Point-to-point and broadcast encryption Key size negotiation (up to 128 bit) Start encryption Accept start of encryption Stop encryption Accept stop of encryption
x x x x x x x x x
Information Requests/Status Requests
Request clock offset information Respond to clock offset requests Send slot offset information Request timing accuracy information Respond to timing accuracy requests Request LM version information Respond to LM version requests Request supported features Respond to supported features requests Request name information Respond to name requests Get link quality Read RSSI
Role Switch
x x x x x x x x x x x x x
Request master/slave switch Accept master/slave switch requests
Detach
x x
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MC71000 Advance Information Preliminary
25
Functionality Overview Table 10. Overview of Link Manager Features (Continued)
ROM V0.92 and ROM V2.01 Planned Future Features Support Not Currently Planned
Feature
Detach connection
Hold Mode
x
Request hold mode Respond to hold mode requests Force hold mode Accept forced hold mode
Sniff Mode
x x x x
Request sniff mode Respond to sniff mode requests Request un-sniff Accept un-sniff requests
Park Mode
x x x x
Request park mode Respond to park mode request Set up broadcast scan window Accept change to the broadcast scan window Modify beacon parameters Accept modification of beacon parameters Request unpark using PM_ADDR Request unpark using BD_ADDR Slave requested unpark Accept unpark using PM_ADDR Accept unpark using BD_ADDR
Power Control
x x x x x x x x x x x
Request to increase power Request to decrease power Respond when max power reached Respond when minimum power reached
x x x x
Link Supervision Timeout
Set link supervision timeout value Accept link supervision timeout setting
x x
Quality of Service
Channel quality driven change between DM and DH packet types
x
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Supported HCI Commands Table 10. Overview of Link Manager Features (Continued)
ROM V0.92 and ROM V2.01 Planned Future Features Support Not Currently Planned
Feature
Force/accept forced change of Quality of Service (QoS) Request/accept change of QoS
x2 x2
Multi-Slot Packages
Allow maximum number of slots to be used Request maximum number of slots to be used Accept request of maximum number of slots to be used
Paging Scheme
x x x
Request page mode to use Accept suggested page mode Request page scan mode to use Accept suggested page scan mode
Test Mode
x x x x
Activate test mode (as tester) Enable test mode (as DUT) and ability to accept activation of test mode Ability to reject activation of test mode if test mode is disabled Control test mode Ability to reject test mode control commands if test mode is disabled x x x
x
x
1.ROM V2.0 is the label assigned to the production-ready, qualified iteration of ROM Version 0.92. There is no plan for a ROM V1.0. 2.ROM Version 0.92 supports Best-Effort Quality of Service (QoS) only. The Guaranteed and No Traffic QoS types are features planned for ROM Version 3.0.
9 Supported HCI Commands
The HCI provides a command interface to the baseband controller and link manager, and access to hardware status and control registers. This interface provides a uniform method of accessing the Bluetooth baseband capabilities. Table 11 shows the currently supported HCI commands. The commands are divided into the following major groupings: link control, link policy, host/baseband, events, informational parameters, status parameters, and testing. The following list shows some of the key features of the HCI: * * * * 23- and 79-channel frequency hopping Supports all connection types Supports all packet types Host controller HCI flow control
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MC71000 Advance Information Preliminary
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Supported HCI Commands
* * * * * * *
Authentication and pairing Change packet type Encryption Master/slave role switch Hold/sniff modes Radio TX power status and control Test modes
Table 11. HCI Commands and Events
HCI Command Name Currently Supported ROM 3.0 Not Supported
Link Control Commands
HCI_Inquiry HCI_Inquiry_Cancel HCI_Periodic_Inquiry_Mode HCI_Exit_Periodic_Inquiry_Mode HCI_Create_Connection HCI_Disconnect HCI_Accept_Connection_Request HCI_Reject_Connection_Request HCI_Change_Connection_Packet_Type HCI_Add_SCO_Connection HCI_Remote_Name_Request HCI_Read_Remote_Supported_Features HCI_Read_Clock_Offset HCI_Read_Remote_Version_Information HCI_Authentication_Requested HCI_Link_Key_Request_Reply HCI_Link_Key_Request_Negative_Reply HCI_Pin_Code_Request_Reply HCI_Pin_Code_Request_Negative_Reply HCI_Change_Connection_Link_Key HCI_Master_Link_Key HCI_Set_Connection_Encryption
Link Policy Commands
X X X X X X X X X X X X X X X X X X X X X X
HCI_Read_Link_Policy_Settings HCI_Write_Link_Policy_Settings HCI_Switch_Role HCI_Role_Discovery HCI_Read_Link_Policy_Settings HCI_Write_Link_Policy_Settings HCI_Hold_Mode HCI_Sniff_Mode
X X X X X X X X
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Supported HCI Commands Table 11. HCI Commands and Events (Continued)
HCI Command Name Currently Supported ROM 3.0 Not Supported
HCI_Exit_Sniff_Mode HCI_Park_Mode HCI_Exit_Park_Mode HCI_QoS_Setup
X X X X
Host/Baseband Commands
HCI_Read_Scan_Enable HCI_Write_Scan_Enable HCI_Read_Page_Scan_Activity HCI_Write_Page_Scan_Activity HCI_Read_Inquiry_Scan_Activity HCI_Write_Inquiry_Scan_Activity HCI_Read_Number_Of_Supported_IAC HCI_Read_Current_IAC_LAP HCI_Write_Current_IAC_LAP HCI_Read_Connection_Accept_Timeout HCI_Write_Connection_Accept_Timeout HCI_Read_Page_Timeout HCI_Write_Page_Timeout HCI_Flush HCI_Read_Automatic_Flush_Timeout HCI_Write_Automatic_Flush_Timeout HCI_Set_Event_Mask HCI_Set_Event_Filter HCI_Reset HCI_Read_Class_of_Device HCI_Write_Class_of_Device HCI_Read_Num_Broadcast_Retransmissions HCI_Write_Num_Broadcast_Retransmissions HCI_Read_Link_Supervision_Timeout HCI_Write_Link_Supervision_Timeout HCI_Read_Voice_Setting HCI_Write_Voice_Setting HCI_Read_SCO_Flow_Control_Enable HCI_Write_SCO_Flow_Control_Enable HCI_Host_Buffer_Size HCI_Set_Host_Controller_To_Host_Flow_Control HCI_Host_Number_Of_Completed_Packets HCI_Read_Authentication_Enable HCI_Write_Authentication_Enable HCI_Read_PIN_Type HCI_Write_PIN_Type
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
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Supported HCI Commands Table 11. HCI Commands and Events (Continued)
HCI Command Name Currently Supported ROM 3.0 Not Supported
HCI_Read_Stored_Link_Key HCI_Write_Stored_Link_Key HCI_Delete_Stored_Link_Key HCI_Read_Encryption_Mode HCI_Write_Encryption_Mode HCI_Read_Hold_Mode_Activity HCI_Write_Hold_Mode_Activity HCI_Read_Transmit_Power_Level HCI_Read_Page_Scan_Mode HCI_Write_Page_Scan_Mode HCI_Read_Page_Scan_Period_Mode HCI_Write_Page_Scan_Period_Mode
X X X X X X X X X X X X
Informational Parameters
HCI_Read_BD_ADDR HCI_Read_Buffer_Size HCI_Read_Local_Supported_Features HCI_Read_Country_Code HCI_Read_Local_Version_Information
Status Parameters
X X X X X
HCI_Read_Failed_Contact_Counter HCI_Reset_Failed_Contact_Counter HCI_Get_Link_Quality HCI_Read_RSSI
Testing
X X X X
HCI_Read_Loopback_Mode HCI_Read_RSSI HCI_Enable_Device_Under_Test_Mode
X X X
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Supported HCI Commands
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HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. The
Bluetooth trademarks are owned by their proprietor and used by Motorola, Inc., under license. The ARM POWERED logo is the registered trademark of ARM Limited. ARM7 and ARM7TDMI-S are trademarks of ARM Limited. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/ Affirmative Action Employer. (c) Motorola, Inc. 2002
MC71000TB/D
Preliminary


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